Vicom Systems FC-FC3 Uživatelský manuál stáhnout pdf (Strana 43)

CONFIDENTIAL [AK8999A/AW/AD]

MS1600-E-00 2014/05

- 43 -

16.

Serial Interface Description

The data of EEPROM and control register (volatile memory) in the AK8999A can be written and read through a

2-wire serial interface on CSCLK pin and VOUT pin. When CSCLK = High is maintained beyond a definite

period of time (1.0msec), VOUT output will change from the Analog output to SDI/O (Serial data I/O).

And data is captured from VOUT synchronously with the rising edge of CSCLK after SDI/O shift. Input data

contains three instruction bits (I2 - I0), five address bits (A4 - A0) and eight data bits (D7 - D0). Provide the data

in the order of I2 → I0 → A4 → A0 → D7 → D0. And when CSCLK=Low is maintained beyond a definite

period of time (0.5msec), VOUT output will return from SDI/O to the Analog output.

On the WRITE instruction, allow 5msec or more write time for EEPROM and 10μsec or more write time for the

control register (see 7) Digital AC Characteristics in the Electrical Characteristics). For the READ instruction,

data is written up to 8CLK for CSCLK and the data output starting at the rising edge of 9CLK is read out.

1) Data Configuration

Configuration of data written to or read out through the serial interface is shown below. There are 16 specific bits

of data in total comprised of three instruction bits, five address bits and eight data bits.

Instruction Address Data

I2 I1 I0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

Data input direction

2) Description of Instructions

Instruction codes are summarized below.

Code

Note

)

Instruction Description

I2 I1 I0

1 1 0 EEPROM read

(Read Mode)

Read out the data written in the EEPROM

1 0 1 EEPROM write

(Write Mode)

Write data to the EEPROM. Write time (from 16

CSCLK

rising edge to CSCLK falling edge) requires 5msec or more.

EEPROM

batch write

(Write Mode)

If the 1Fh address is written, input data is written to all

addresses except for 1Eh. Write time (from 16

CSCLK rising

edge to CSCLK falling edge) requires 10msec or more.

0 1 0 Control reg. read

(Read Mode)

Read out the data written in the control register.

0 0 1 Control reg. write

(Write Mode)

Write the data to the control register. Write time (from 16

CSCLK rising edge to CSCLK falling edge) requires 10μsec

or more.

Note) Instructions other than this are prohibited.

1 2 ... 38 39 40 41 42 43 44 45 46 47 48 ... 67 68

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